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2 variable K-

Interview Questions. Main, FPGA, Digital Fundamentals

Resources

Clock Domain Crossing Discussion with

rtl & testbench example.

Rate change (asynchronous) FIFO & fifo depth calculation.

Half-adder , Full-adder , 4-bit binary adder , adder-subtractor circuit, overflow with rtl & testbench. Binary Multiplier, Parity error TT

Arithmetic, logical, shift micro-operations . Stack organization, LIFO, RPN discussion.

VHDL rtl - Synchronous flip-flop , latch, shim to improve timing and counter example

RTL coding guidelines. ICG cell, Assertions, $assertkill, levels.

Digital design Interview questions.

FPGA Interview. FPGA flow.

Graduate studies in US

Pipeline vs. Parallel processing.

Clock Domain Crossing Discussion with

rtl & testbench example.

Rate change (asynchronous) FIFO & fifo depth calculation.

Half-

VHDL rtl -

Digital design Interview questions.

FPGA Interview. FPGA flow.

Graduate studies in US

Pipeline vs. Parallel processing.

1. F(x,y,z) = (0,1,6,7) - Minimization, on this page.

2. F(x,y,z) = (0,1,4,5,6,7) - Minimization from here.

3. F(x,y,z) = (3,4,6,7) - Minimization from here.

4. F(x,y,z) = (0,1,2,3,4,5,6,7) - Minimization from here.

A solved example of 2 variable k-

F(x,y)=sum(0,2,3)

0

1

0

1

x

y

x’y’ =1

xy’ = 1

xy = 1

Minimization solution to above function.

= y’(x + x’) + xy + xy’ = y’ + x (y+y’) = y’ + x

K-

Introduction to Verilog RTL

Verilog Operators.

Initial Statements in verilog.

Clock and Reset generation.

Blocking vs. Non-blocking Statements.

Conditional Statements & ‘always’ block.

Counter Implementation.

File Operations - $fopen, $fclose, $fdisplay, $fscanf

Read binary or hex format files - $readmemh, $readmemb.

FOR Loop use in verilog code example

Verilog Operators.

Initial Statements in verilog.

Clock and Reset generation.

Blocking vs. Non-

Conditional Statements & ‘always’ block.

Counter Implementation.

File Operations -

Read binary or hex format files -

FOR Loop use in verilog code example