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Verilog Tutorial.
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Verilog Tutorial.
Top Tech Topics @FCD
 K-map - 2,3,4,5 var & Prime Implicant discussion
 Verilog - learn with examples
 Interview questions and hints
Verilog testbench to generate random numbers and use of $fdisplay to store it in a text file.
Generating random numbers and $fdisplay in Verilog testbench.
~\Desktop\FCD\downloads\fc_v\random_fc.v.html // Test Bench for generating random numbers
module random_tb ();

integer seed;
integer out;
integer i ;

initial begin
  out = $fopen("rand.vec","w");
  $fdisplay(out, "seed = %h, 1st random number in hexadecimal = 0x%h", seed, $random(seed));
  $fdisplay(out, "seed = %h, 2nd random number in hexadecimal = 0x%h", seed, $random(seed));
  $fdisplay(out, "seed = %h, 3rd random number in hexadecimal = 0x%h", seed, $random(seed));
  $fdisplay(out, "seed = %h, 4th random number in hexadecimal = 0x%h", seed, $random(seed));
  $fdisplay(out, "seed = %h, 5th random number in hexadecimal = 0x%h", seed, $random(seed));
end

endmodule
Contents of the output text ‘rand.vec’ is displayed below.
seed = 23980634, 1st random number in hexadecimal  = 0x12153524
 seed = 92153206, 2nd random number in hexadecimal = 0xc0895e81
 seed = 40895ccf,  3rd random number in hexadecimal  = 0x8484d609
 seed = 0484d4c4, 4th random number in hexadecimal  = 0xb1f05663
 seed = 31f054f5,  5th random number in hexadecimal  = 0x06b97b0d
Results are discussed below:-
Misc. Verilog RTL examples:-

Binary to Gray Code conversion
 File read write operations.
 Clock domain crossing.
 Half-adder, Full-adder, Tri-state buffer .
 Verilog testbench to validate half-adder, full-adder and tri-state buffer.
VERILOG HOME
Hardware components of a smart-phone.
 CPU or processor of a cell phone.
 Operating System or simply O/S
 RAM, a type of memory and SD Memory
 Applications for direct user interface.
 PIXELS for resolution of screen.
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