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Verilog Tutorial.

Metastability is a condition on the output signal of a flip-flop due setup or hold time violation on the digital input signal.

 

A metastable signal does not represent a high ’1’ or a low ’0’ and results in unstable output or a glitch to the digital circuit.    

 

Following block diagram can used to implement clock domain crossing for phase offset clocks.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Link to verilog rtl for clock domain crossing.

 

Check below the block diagram for clock domain crossing

Clock domain crossing discussion

Verilog code for clock domain crossing   

 

Double clocking is generally implemented to avoid the metastability arising from setup or hold time violations.

 

 

Verilog code for clock domain crossing  and RTL test-bench
Clock Crossing Async FIFO Half Adder Full Adder Binary Adder Overflow Overflow Det Adder-Subtractor Multiplier Parity check RTL guidelines NAND to INVERTER VHDL RTL Arith Micro-ops Stack Org Parallel proc. Pipeline proc CMOS Intro
Misc. Verilog RTL examples:-

Binary to Gray Code conversion
 File read write operations.
 Clock domain crossing.
 Half-adder, Full-adder, Tri-state buffer .
 Verilog testbench to validate half-adder, full-adder and tri-state buffer.
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Clock Domain Crossing Discussion with
 rtl & testbench example.
Rate change(asynchronous) FIFO design and fifo depth calculation.
Half-adder, Full-adder, 4-bit binary adder , adder-subtractor circuit, overflow with rtl & testbench. Binary Multiplier, Parity error TT
 Arithmetic, logical, shift micro-operations. Stack organization, LIFO, RPN discussion.
 VHDL rtl - Synchronous flip-flop, latch, shim to improve timing and counter example
RTL coding guidelines. ICG cell, Assertions, $assertkill, levels.
Digital design Interview questions.
FPGA Interview. FPGA flow.
 Guide to Graduate studies in US
Pipeline vs. Parallel processing.
Top Tech Topics @FCD
K-map - 2,3,4,5 var & PrimeImplicant discussion
Verilog - learn with examples
Interview questions and hints