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Verilog Initial stmts IF-ELSE Case stms Readmemh Function Testbench Binary to Gray Clock Crossing Half-adder Full-adder Tristate buffer Adder tb Counter_enable Blocking Operators Shift LSR Random Nos Sync RAM Verilog Tutorial

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Verilog Tutorial.
Tri-state buffer discussion
Verilog RTL example for tri-state buffer.
Tri-state buffer test-bench

// Tristate Buffer

module tristate_buffer(input_x, enable, output_x);

input input_x;

input enable;

output output_x;

assign output_x = enable ? input_x : 'bz;

endmodule

---------------------

Tri-State Buffer

----------------------

input_x = 0, enable = 0, output_x = z

input_x = 1, enable = 0, output_x = z

input_x = 1, enable = 1, output_x = 1

input_x = 0, enable = 1, output_x = 0

Misc. Verilog RTL examples:-

Binary to Gray Code conversion
 File read write operations.
 Clock domain crossing.
 Half-adder, Full-adder, Tri-state buffer .
 Verilog testbench to validate half-adder, full-adder and tri-state buffer.
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