Chip Designing for ASIC/ FPGA Design engineers and Students

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LIFO, Stack Organization, SP and RPN.

In digital computing, the location of memory which is set aside for holding data temporarily can be called as Stack. The order in which data is retrieved from stack is Last In First Out (LIFO) method.

LIFO:- It’s a method in which the last data entry written in stack is the first entry retrieved during read.

Stack Pointer :- The pointer which track’s the location of stack memory to write or read data from is know as Stack Pointer (SP)

PUSH and POP :- The operation of inserting a value in stack is called PUSH. On the contrary, the operation of retrieving a value is called POP.
In digital design, the stack can be implemented as a memory location or as a set of registers.

Reverse Polish Notation (RPN) for evaluating arithmetic equations is discussed here.

REVERSE POLISH NOTATION (RPN)

Different ways of representing an arithmetic expression is shown below.

A * B - Inflix notation, most common.
*AB - Polish Notation. Operator is placed before the operands.
AB* - Reverse Polish Notation. Operator is placed after the operand.  

In RPN digital operations the expressions are operated from left to write and evaluated in accordance with operator precedence.  

Role of stack in RPN:
During the procedure of conversion of arithmetic expressions into RPN, the operands are pushed into the stack in order of processing.




Examples of evaluating a reverse polish expression.

RPN:-
AB*C+

Equivalent arithmetic expression:-

Step 1:- (A*B)C+
Step 2:- (A*B) + C

Misc. Verilog RTL examples:-

Binary to Gray Code conversion
File read write operations.
Clock domain crossing.
Half-adder, Full-adder, Tri-state buffer .
Verilog testbench to validate half-adder, full-adder and tri-state buffer.

VERILOG HOME

Interview Questions. Main, FPGA, Digital Fundamentals

Resources

Digital design resources
Clock Domain Crossing Discussion with
rtl & testbench example.

Rate change(asynchronous) FIFO design and fifo depth calculation.

Half-adder, Full-adder, 4-bit binary adder , adder-subtractor circuit, overflow with rtl & testbench. Binary Multiplier, Parity error TT
Arithmetic, logical, shift micro-operations. Stack organization, LIFO, RPN discussion.
VHDL rtl - Synchronous flip-flop, latch, shim to improve timing and counter example

RTL coding guidelines. ICG cell, Assertions, $assertkill, levels.
Digital design Interview questions.
FPGA Interview. FPGA flow.
Guide to Graduate studies in US

Pipeline vs. Parallel processing.