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Representation of Boolean Function in Sum of Minterms
Two step approach to represent three variables in term of Minterms:-
Step1: Represent the Minterm needs to be considered for the function by ‘1’
Step2: Take the OR of all Minterms to represent the function.
The Function of Minterms F = x’y’z + x’yz’ + xy’z + xyz’ + xyz
Example: Represent F = x + yz + xy in Sum of Product terms.
F = x (y + y’)(z + z’) + yz (x + x’) + xy (z + z’)
= xyz + xyz’ + xy’z + xy’z’ + xyz + x’yz + xyz + xyz’
= xyz + xyz’ + xy’z + xy’z’ + x’yz
Answer.
x
y
z
Minterm in Function
Minterms
0
0
0
0
0
0
1
1
x’y’z
0
1
0
1
x’yz’
0
1
1
0
1
0
0
0
1
0
1
1
xy’z
1
1
0
1
xyz’
1
1
1
1
xyz
The Function of Minterms F is given below
Digital Logic fundamentals topics @ fcd
Digital basics tutorial
Binary number discussion, 1 and 2 complement discussion,
Binary arithmetic, Signed Magnitude, overflow, examples
Gray coding, Binary coded digital (BCD) coding, BCD addition
Digital logic gates basic (AND, OR, XOR, NOT) and derived (NAND, NOR and XNOR). Drive XOR from NAND gates. Drive XOR from NOR gates
Discussion of Boolean Algebra with examples.
Duality Principle, Huntington Postulates, Theorems of Boolean Algebra - discussion with examples, Boolean Functions, Canonical and Standard Forms, Minterms and Maxterms
Sum of Minterms, Product of Maxterms or Canonical Forms,
Karnaugh map or K-map discussion 2, 3, ,4 and 5 var’s
Digital basics tutorial
Binary number discussion, 1 and 2 complement discussion,
Binary arithmetic, Signed Magnitude, overflow, examples
Gray coding, Binary coded digital (BCD) coding, BCD addition
Digital logic gates basic (AND, OR, XOR, NOT) and derived (NAND, NOR and XNOR). Drive XOR from NAND gates. Drive XOR from NOR gates
Discussion of Boolean Algebra with examples.
Duality Principle, Huntington Postulates, Theorems of Boolean Algebra -
Karnaugh map or K-
Resources
Digital design resources
Clock Domain Crossing rtl & testbench. Rate change (asynchronous) FIFO design
Half-adder , Full-adder , 4-bit binary adder , adder-sub circuit, overflow with rtl & testbench. Binary Multiplier, Parity error TT, Arithmetic, logical, shift micro-ops . Stack organization, LIFO, RPN discussion. RTL coding guidelines. ICG cell, Assertions, $assertkill, levels.
Digital design resources
Clock Domain Crossing rtl & testbench. Rate change (asynchronous) FIFO design
Half-