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Prime Implicants discussion with help of Karnaugh map (K-map) - Contd.

Gate level Minimization Example. Refer prime implicants basics from here  

Example :-   Consider a function F (x, y, z, w) of 11 Minterms shown in Truth Table

Truth Table

So Following are the Four Essential Prime Implicants.

z’w, xz’, xw, x’zw’

Next step is to map remaining two(7 and 10)  minterms in all possible combinations.

for Minterm 7,

yw or yz

for Minterm 10,

xy or yz

So the final simplified solutions of the function are

Solution 1.   z’w + xz’+ xw + x’zw’ + yw + xy

Solution 2.   z’w + xz’+ xw + x’zw’ + yz

K-map location number
x
y
z
w
Output Function
0
0
0
0
0
1
0
0
0
1
x’y’z’w
2
0
0
1
0
x’y’zw’
3
0
0
1
1
4
0
1
0
0
5
0
1
0
1
x’yz’w
6
0
1
1
0
x’yzw’
7
0
1
1
1
x’yzw
8
1
0
0
0
xy’z’w’
9
1
0
0
1
xy’z’w
10
1
0
1
0
xy’zw’
11
1
0
1
1
12
1
1
0
0
xyz’w’
13
1
1
0
1
xyz’w
14
1
1
1
0
xyzw’
15
1
1
1
1
xyzw

K– map plot of 11 Minterms

There are Four essential terms for the function in discussion. The essential terms are shown within squares in the Truth Table.

zw

xy

Misc. Verilog RTL examples:-

Binary to Gray Code conversion
 File read write operations.
 Clock domain crossing.
 Half-adder, Full-adder, Tri-state buffer .
 Verilog testbench to validate half-adder, full-adder and tri-state buffer.
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