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In digital communications, an extra bit is sometimes appended to the message to make the ‘logic high’ bit count even or odd. This extra bit is know as parity bit and used for error detection.
The transmitter is responsible for generating the parity bit and receiver is responsible for detecting the message including the parity bit. If message doesn’t meet the parity check an error flag is generated and transmitter is requested to re-transmit the packet.
The transmitter is responsible for generating the parity bit and receiver is responsible for detecting the message including the parity bit. If message doesn’t meet the parity check an error flag is generated and transmitter is requested to re-
The block diagram implementation of generator and checker shows that the circuit requires 2 XOR gates at the parity generation side of transmitter and 3 XOR gates at the receiver side of parity checker.
Truth tables of parity generation and parity checker are discussed here.
Truth tables of parity generation and parity checker are discussed here.
Discussion of circuit
Circuit Level implementation of parity generator and parity checker.
Lets discuss the circuit diagram of Parity generator and parity checker below.
Parity Generation
Parity Checking
