Chip Designing for ASIC/ FPGA Design engineers and Students

FULLCHIPDESIGN

Digital-logic Design...  Dream for many students… start learning front-end…

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Parity Generation Truth Table

Parity Check Truth Table

PRE stands for Parity Receive Error check.

Misc. Verilog RTL examples:-

Binary to Gray Code conversion
File read write operations.
Clock domain crossing.
Half-adder, Full-adder, Tri-state buffer .
Verilog testbench to validate half-adder, full-adder and tri-state buffer.

VERILOG HOME

Parity Generation circuit and Parity checker circuit from here

Parity Generation circuit and Parity checker circuit from here

Resources
Digital design resources
Clock Domain Crossing rtl & testbench.
Rate change (asynchronous) FIFO design and fifo depth calculation.
Half-adder, Full-adder, 4-bit binary adder , adder-subtractor circuit, overflow with rtl & testbench. Binary Multiplier, Parity error TT, Arithmetic, logical, shift micro-operations. Stack organization, LIFO, RPN discussion.
RTL coding guidelines. ICG cell, Assertions, $assertkill, levels.
Digital design Interview questions.
FPGA Interview. FPGA flow.
Guide to Graduate studies in US
Pipeline vs. Parallel processing.

LTE - Long Term Evolution topics from here

Arithmetic, logical, shift micro-operations, Overflow

Half-Adder, Full-Adder, Adder-Subtractor.
Verilog code -
Half-Adder, Full-Adder

Interview Questions. Main, FPGA, Digital Fundamentals