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Parallel Processing.  Next topic Pipeline Processing

In this implementation the data is computed simultaneously using multiple instantiation of same digital circuit.

Advantages:-
Faster execution time., so higher throughput.  
Disadvantages:-
More hardware required, also more power requirements. Not good for low power and mobile devices.

There are different ways to classify parallel processing in modern computers.

According to M..J Flynn.  Most computers fetch instructions from memory and constitutes  instruction stream (IS). The other category in data stream (DS) which involves operations on data.




Flynn's classified digital computers in following categories:-

1. SISD - Single instruction stream and single data stream.

In this architecture only 1 processor,  1 memory and 1 control units are implemented. In this 1 instruction can be executed at any time. So the instructions are held at input and serially pushed one after another.   

2. SIMD - Single instruction stream and multiple data stream.

In this architecture many processor’s are implemented to work with single control unit. The multiple memory module needs to be implemented to support each control unit independently.  

3. MISD - Multiple instruction stream and single data stream.

Theoretically this architecture implements many processor’s to work with independent control units. The single memory module is implemented to support only one data path. Not logical to implement practically as a product.    

4. MIMD - Multiple instruction stream, multiple data stream.




In this architecture, many processor’s are implemented to work with multiple control units to process multiple instructions in parallel. The multiple memory modules are implemented to support parallel data streams.  
According to Flynn, we can classify Pipeline processing as an efficient implementation of hardware to process multiple instructions sequentially.

Resources

Digital design resources
Clock Domain Crossing Discussion with
rtl & testbench example.

Rate change(asynchronous) FIFO design and fifo depth calculation.

Half-adder, Full-adder, 4-bit binary adder , adder-subtractor circuit, overflow with rtl & testbench. Binary Multiplier, Parity error TT
Arithmetic, logical, shift micro-operations. Stack organization, LIFO, RPN discussion.
VHDL rtl - Synchronous flip-flop, latch, shim to improve timing and counter example

RTL coding guidelines. ICG cell, Assertions, $assertkill, levels.
Digital design Interview questions.
FPGA Interview. FPGA flow.
Guide to Graduate studies in US

Pipeline vs. Parallel processing.

Misc. Verilog RTL examples:-

Binary to Gray Code conversion
File read write operations.
Clock domain crossing.
Half-adder, Full-adder, Tri-state buffer .
Verilog testbench to validate half-adder, full-adder and tri-state buffer.

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Interview Questions. Main, FPGA, Digital Fundamentals