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Chip Designing for ASIC/ FPGA Design engineers and Students
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Digital-logic Design... Dream for many students… start learning front-end…
Topics @TYH :- 4G LTE Tutorial, Inside Smart-Phone , Cloud Computing
4 -
Truth Table
4 variable K– map for the truth -
K-
x
y
z
w
Output Function
0
0
0
0
0
x’y’z’w’
1
0
0
0
1
x’y’z’w
2
0
0
1
0
x’y’zw’
3
0
0
1
1
x’y’zw
4
0
1
0
0
X’yz’w’
5
0
1
0
1
x’yz’w
6
0
1
1
0
x’yzw’
7
0
1
1
1
x’yzw
8
1
0
0
0
xy’z’w’
9
1
0
0
1
xy’z’w
10
1
0
1
0
xy’zw’
11
1
0
1
1
xy’zw
12
1
1
0
0
xyz’w’
13
1
1
0
1
xyz’w
14
1
1
1
0
xyzw’
15
1
1
1
1
xyzw
00
01
11
10
3
2
xy
zw
00
01
11
10
4
5
7
6
12
13
15
14
8
9
10
11
0
1
Interview Questions. Main, FPGA, Digital Fundamentals