Digital Logic

Q. Give two ways of converting a two input NAND gate to an inverter. Hint: click here . Drive XOR from NAND gates. Drive XOR from NOR gates

Q. How to calculate depth of FIFO for rate change implementation ? Answer: FIFO design example

Q. Simplify Boolean Functions F = xyz + x’y + xyz’. Answer: click here

Q. Represent F = x + yz + xy in Sum of Product terms.

Q. Represent F = x + yz + xy in Product of Sum terms. Answer

Q. What do you mean by prime Implicants? What are Essential Terms ? Why it is required ? Click here

Q. Consider a function F (x, y, z, w) of 11 Minterms shown in Truth Table

Truth Table . Gate level minimization :- Answer click here

More digital basics interview questions for entry-level jobs. Click here

Interview Questions for jobs in FPGA/ASIC

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Getting through interviews is always a challenging task and requires thorough preparation . Here is a list of probable questions that may appear in an interview related to RTL skills.

RTL

Q. How do you differentiate between coding in C/C++ and at RTL (Register Transfer Level) ? Hint: In RTL logic is divided into sequential and combinational logic blocks.
Q. How do you differentiate between wires and registers in Verilog ?Hint: Registers are used to store values and wires are used only for connections. D Flip-flops in Digital design generally represents registers.
Q. How do you diff between blocking vs. non-blocking statements in Verilog ? Click here
Q. Sensitivity lists declaration in always block for sequential and combinational logic?
Q. How to implement tri-state logic in verilog? click here
Q. Differentiate between tasks and functions in Verilog?
Q. How to implement Half-adder and full-adder in RTL? click here
Q. When the latches are inferred in RTL ? Hint : click here

Q. How do you differentiate between ‘==‘ and ‘= = =‘ logic? Hint : ’===’ are not synthesizable and used in simulations.

FPGA

Q. How to generate clocks on FPGA? Hint : Should use Digital Clock Manager’s for clock generations.
Q. Gated clocks in FPGA implementations ? Hint: No gated clocks in FPGA implementations.
Click Here for more fpga interview questions.

Static Timing Analysis

Q. Setup time and hold time in digital circuits.
Q. False path in FPGA’s, Critical path, Negative slack, Jitter vs. clock skew .
Q. Routing delay, Flop to out delay, Flop to flop delay, Pad to flop delay, Board delay.
Q. Knowledge of Synthesis and layout constraints.

Behavioral

Q. How will you allocate your time between architecture, coding, and verification?
Q. Checkout the company web pages and on search engines about the latest technology and products.
Q. Prepare a set of questions to ask the interviewer about the group and or company.
Finally … relax and chill out for few hours before the interview …

Other sections related to digital design

RF basics - RF fundamentals discussion
SignaltoNoise(SNR), NoiseFactor(F), NoiseFigure(NF), Dynamic Range (DR), Minimum Detectable Signal (MDS),
Intermodulation (IM) distortion, Second order (IP2) & Third order (IP3) intermodulation products, IP3 (Third Order Intercept) plot
Desensitization, Cross-modulation, Spurious outputs, Gain control, Noise

Resources

Clock Domain Crossing Discussion with rtl & testbench .
Rate change (asynchronous) FIFO design and fifo depth calculation.

Half-adder & Full-adder circuit discussion with rtl & testbench

VHDL rtl - Synchronous flip-flop, latch, shim to improve timing and counter example

Q. Do you understand Pipeline Architecture? Differentiate it from Parallel processing. Most important design question for most interviews.

RTL Design engineers

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Interview Questions. Main, FPGA, Digital Fundamentals

Misc. Verilog RTL examples:-

Binary to Gray Code conversion
File read write operations.
Clock domain crossing.
Half-adder, Full-adder, Tri-state buffer .
Verilog testbench to validate half-adder, full-adder and tri-state buffer.

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