Chip Designing for ASIC/ FPGA Design engineers and Students

FULLCHIPDESIGN

Digital-logic Design...  Dream for many students… start learning front-end…

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Half-adder is represented in the diagram below.  Its used to calculate sum of 2 bits using a circuit composed of one AND gate and one XOR gate.

Truth table for Half-adder is below:

Verilog RTL example for Half-adder

Full-Adder, Adder-Subtractor. Verilog code - half-adder, full-adder

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Cloud Computing
Inside Smart Phones

Overflow

Binary adder-subtractor circuit

Full-adder RTL & test-bench

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K-map - 2,3,4,5 var & Prime Implicant discussion

Verilog - learn with examples

Interview questions and hints

Resources for digital design

Clock Domain Crossing Discussion with rtl & testbench example.
Rate change(asynchronous) FIFO design and fifo depth calculation.
Half-adder, Full-adder, 4-bit binary adder , adder-subtractor circuit, overflow with rtl & testbench. Binary Multiplier, Parity error TT
Arithmetic, logical, shift micro-operations. Stack organization, LIFO, RPN discussion.
VHDL rtl - Synchronous flip-flop, latch, shim to improve timing and counter example
RTL coding guidelines. ICG cell, Assertions, $assertkill, levels.
Digital design Interview questions.
FPGA Interview. FPGA flow.
Guide to Graduate studies in US
Pipeline vs. Parallel processing.

Interview Questions. Main, FPGA, Digital

Arithmetic, logical, shift micro-operations, Overflow

Misc. Verilog RTL examples:-

Binary to Gray Code conversion
File read write operations.
Clock domain crossing.
Half-adder, Full-adder, Tri-state buffer .
Verilog testbench to validate half-adder, full-adder and tri-state buffer.

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