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Verilog Tutorial.

XOR from NAND gates

XOR Truth Table:-

NAND Truth Table

Step 2 involves Invert of A and invert of B. check circuit for nand to inverter

So the complete circuit for XOR using NAND gates is shown below.

Diagram here

Clock Crossing Async FIFO Half Adder Full Adder Binary Adder Overflow Overflow Det Adder-Subtractor Multiplier Parity check RTL guidelines NAND to INVERTER VHDL RTL Arith Micro-ops Stack Org Parallel proc. Pipeline proc CMOS Intro
Some of the most important interview questions includes the conversion of gates. Here at FCD we have discussed following conversions.
NAND to Inverter
 XOR from NAND discussed on this page.
 XOR from NOR.

In this page we are going to cover XOR from NAND gate. Lets start the discussion with truth tables of XOR and NAND.
A
B
Y
0
0
0
0
1
1
1
0
1
1
1
0
A
B
Y
0
0
0
0
1
1
1
0
1
1
1
0
From Digital Basics section we know the equations for XOR and NAND gates. The equations are also shown below:-

XOR equation = A’B + AB’
 NAND equation = A’ + B’
Following are the steps to drive XOR only using NAND gates
First reformat the XOR equation.
Step 1 :- A'B + AB' = [(A+B')' + (A'+B)'] using theorems T7, T8 and T9
 Step 2 :- [((A')'+B')' + (A' + (B')')'] using theorems T7, T8 and T9
Misc. Verilog RTL examples:- Binary to Gray Code conversion File read write operations. Clock domain crossing. Half-adder, Full-adder, Tri-state buffer . Verilog testbench to validate half-adder, full-adder and tri-state buffer. VERILOG HOME
Misc. Verilog RTL examples:-

Binary to Gray Code conversion
 File read write operations.
 Clock domain crossing.
 Half-adder, Full-adder, Tri-state buffer .
 Verilog testbench to validate half-adder, full-adder and tri-state buffer.
 VERILOG HOME
Hot Topics @FCD
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Inside Smart Phones
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Binary adder-subtractor
Full-adder RTL & test-bench