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RTL Design engineers
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Digital Logic Gates symbols and truth table.
Discussion of Boolean Algebra
.
Duality Principle
and
Huntington Postulates
.
Theorems of Boolean Algebra -
discussion
.
Discussion of Boolean Functions.
Boolean Functions using truth tables.
Implementation of Boolean Functions using gates.
Exercise to minimize Boolean Functions.
Representation of Boolean functions in Canonical
and Standard Forms.
Minterms
and
Maxterms
discussion.
Sum of Minterms.
Product of Maxterms or Canonical Forms.
Karnaugh map or K-
map discussion.
Two variables K-
map
(truth table and K-
map plot).
Three variables K-
map
(truth table and K-
map plot).
Four variables K-
map
(truth table and K-
map plot).
Home
Binary Numbers
1s_complement
2s_complement
Binary Subtraction
Binary Sub. Ex's
Sign_magnitude
SignM EX
Gray Coding
BCD coding
Digital gates
NAND NOR & XNOR
Theorems
Boolean Functions
BFunc Examples
Minterm Maxterm
Sum of Minterms
Prdt of Maxterms
2 var K-map
3 var K-map
4 var K-map
5 var K-map
Prime Implicant
PI example
1’s complement discussion
and
2’s complement discussion.
(With examples.)
Binary coding and
Gray coding
. Discussion with
Verilog rtl code example
s
.
BCD coding and step by step addition approach using EXAMPLES
.
Binary Numbers
discussion
.
Decimal to Binary conversions
.
Binary to Decimal
conversions
.
Hexadecimal
conversions.
Complement’s of
binary numbers.
Binary arithmetic and examples.
Binary subtraction and examples.
Signed Magnitude & examples.
BCD (Binary Coded Digital) addition.
Five variables K-
map.
Prime Implicant
and
Gate level minimization
examples.
Misc. Verilog RTL examples:-
Binary to Gray Code conversion
File read write operations.
Clock domain crossing.
Half-
adder
,
Full-
adder
,
Tri-
state buffer
.
Verilog
testbench to validate half-
adder, full-
adder and tri-
state buffer.
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Interview Questions.
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Long Term Evolution
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