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Verilog Tutorial.
Binary Numbers 1s_complement 2s_complement Binary Subtraction Binary Sub. Ex's Sign_magnitude SignM EX Gray Coding BCD coding Digital gates NAND NOR & XNOR Theorems Boolean Functions BFunc Examples Minterm Maxterm Sum of Minterms Prdt of Maxterms 2 var K-map 3 var K-map 4 var K-map 5 var K-map Prime Implicant PI example

Boolean Algebra

 

Duality Principle:

This property of Boolean algebra state that all binary expressions remain valid when following two steps are performed:

Step 1 :  Interchange OR and AND operators.

Step 2 :  Replace all 1’s by 0’s and 0’s by 1’s.

Huntington Postulates

Adding a number to ‘0’ to itself

P1. Postulate:- x + 0 = x

From duality of P1

P2. Postulate:- x * 1 = x

Sum of a number and its complement from a Set is ‘1’

P3. Postulate:- x + x’= 1

From duality of P3

P4. Postulate:- x * x’ = 0

From commutative property of binary numbers we have:-

P5. Postulate:- x + y = y + x

From duality of P5

P6. Postulate:- x * y = y * x

From distributive property of binary numbers we have:-

P7. Postulate:- x(y + z) = xy + xz

From duality of P7

Duality principle, Huntington postulates and Theorems
Refer Boolean Agebra Theorems from here - Theorems
Digital Logic fundamentals topics @ fcd

Digital basics tutorial
 Binary number discussion, 1 and 2 complement discussion,
Binary arithmetic, Signed Magnitude, overflow, examples
Gray coding, Binary coded digital (BCD) coding, BCD addition
Digital logic gates basic (AND, OR, XOR, NOT) and derived (NAND, NOR and XNOR). Drive XOR from NAND gates. Drive XOR from NOR gates
 Discussion of Boolean Algebra with examples.
Duality Principle, Huntington Postulates, Theorems of Boolean Algebra - discussion with examples,
Boolean Functions,
Canonical and Standard Forms, Minterms and Maxterms
Sum of Minterms, Product of Maxterms or Canonical Forms,
Karnaugh map or K-map discussion 2, 3, ,4 and 5 var’s
 Prime Implicant and Gate level minimization examples.
Misc. Verilog RTL examples:-

Binary to Gray Code conversion
 File read write operations.
 Clock domain crossing.
 Half-adder, Full-adder, Tri-state buffer .
 Verilog testbench to validate half-adder, full-adder and tri-state buffer.
VERILOG HOME
Top Tech Topics @FCD
 K-map - 2,3,4,5 var & Prime Implicant discussion
 Verilog - learn with examples
 Interview questions and hints