Gray en Coding Verilog example. Gray to binary to decimal conversion table. Any number from 0 to 100. One bit is allowed to transition between two consecutive numbers. Asynchronous interface, clock crossing, pointers of async fifo reads counters.

Custom Search

Feedback ? Send it to admin@fullchipdesign.com or join me at fullchip@gmail.com

Legal Disclaimer

Chip Designing for ASIC/ FPGA Design engineers and Students

FULLCHIPDESIGN

Digital-logic Design... Dream for many students… start learning front-end…

Legal Disclaimer

Topics @TYH :- 4G LTE Tutorial, Inside Smart-Phone, Cloud Computing

RTL Design engineers

Students & Engineers

FORUM

FORUM

Gray Coding in Digital Design

Some implementation in digital design requires Gray encoding where only one bit is allowed to transition between two consecutive numbers.

Decimal to binary to gray codes from 0-100 are discussed below.

Binary to Gray code mapping for 0 to 10

# Decimal = 0 : Binary = 10'b0000000000 : Gray = 10'b0000000000

# Decimal = 1 : Binary = 10'b0000000001 : Gray = 10'b0000000001

# Decimal = 2 : Binary = 10'b0000000010 : Gray = 10'b0000000011

# Decimal = 3 : Binary = 10'b0000000011 : Gray = 10'b0000000010

# Decimal = 4 : Binary = 10'b0000000100 : Gray = 10'b0000000110

# Decimal = 5 : Binary = 10'b0000000101 : Gray = 10'b0000000111

# Decimal = 6 : Binary = 10'b0000000110 : Gray = 10'b0000000101

# Decimal = 7 : Binary = 10'b0000000111 : Gray = 10'b0000000100

# Decimal = 8 : Binary = 10'b0000001000 : Gray = 10'b0000001100

# Decimal = 9 : Binary = 10'b0000001001 : Gray = 10'b0000001101

# Decimal = 10 : Binary = 10'b0000001010 : Gray = 10'b0000001111

Binary to Gray code mapping for 11 to 50 click here

Binary to Gray code mapping for 50 to 100 click here

Resources
Clock Domain Crossing Discussion with
rtl & testbench example. Rate change (asynchronous) FIFO design and fifo depth calculation. Half-adder, Full-adder, 4-bit binary adder , adder-subtractor circuit, overflow with rtl & testbench. Binary Multiplier, Parity error TT, Arithmetic, logical, shift micro-operations. Stack organization, LIFO, RPN discussion. VHDL rtl - Synchronous flip-flop, latch, shim to improve timing and counter example. RTL coding guidelines. ICG cell, Assertions, $assertkill, levels. Pipeline vs. Parallel processing.

Binary Numbers 1s_complement 2s_complement Binary Subtraction Binary Sub. Ex's Sign_magnitude SignM EX Gray Coding BCD coding Digital gates NAND NOR & XNOR Theorems Boolean Functions BFunc Examples Minterm Maxterm Sum of Minterms Prdt of Maxterms 2 var K-map 3 var K-map 4 var K-map 5 var K-map Prime Implicant PI example

Digital Logic fundamentals topics @ fcd
Digital basics tutorial, Binary number discussion, 1 and 2 complement discussion, Binary arithmetic, Signed Magnitude, overflow, examples
Gray coding, Binary coded digital (BCD) coding, BCD addition
Digital logic gates basic (AND, OR, XOR, NOT) and derived (NAND, NOR and XNOR). Drive XOR from NAND gates. Drive XOR from NOR gates
Discussion of Boolean Algebra with examples.
Duality Principle, Huntington Postulates, Theorems of Boolean Algebra - discussion with examples, Boolean Functions, Canonical and Standard Forms, Minterms and Maxterms, Sum of Minterms, Product of Maxterms or Canonical Forms, Karnaugh map or K-map discussion 2, 3, ,4 and 5 var’s
Prime Implicant and Gate level minimization examples.

Interview Questions. Main, FPGA, Digital Fundamentals

Check out Verilog code to implement Gray Encoding

LTE Long Term Evolution topics.

Check out Verilog code to implement Gray Encoding