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Boolean Functions, equivalent truth table and gate level implementation.
Operator precedence for evaluating Boolean Expressions.
Boolean function example:
Where F1 is a Boolean function of binary variables and binary operators. The binary
variables and operators are specified below
Binary variables = x, y and z
Binary operators = Parentheses, NOT, AND and OR
Solving or minimization of the functions are performed in a particular precedence
shown below
Representation of Boolean function in Truth Table
The truth table above lists all the variables in function as inputs (x, y and z)
and the output of function as column F1. In order to derive a gate level implementation
we will need to analyze all possible combination of inputs and corresponding output.
Digital Logic fundamentals topics @ fcd
Digital basics tutorial
Binary number discussion, 1 and 2 complement discussion,
Binary arithmetic, Signed Magnitude, overflow, examples
Gray coding, Binary coded digital (BCD) coding, BCD addition
Digital logic gates basic (AND, OR, XOR, NOT) and derived (NAND, NOR and XNOR). Drive XOR from NAND gates. Drive XOR from NOR gates
Discussion of Boolean Algebra with examples. Duality Principle, Huntington Postulates, Theorems of Boolean Algebra - discussion with examples, Boolean Functions, Canonical and Standard Forms, Minterms and Maxterms Sum of Minterms, Product of Maxterms or Canonical Forms, Karnaugh map or K-map discussion 2, 3, ,4 and 5 var’s
Prime Implicant and Gate level minimization examples.











A boolean function is an expression consisting for binary variables, binary operators and constants (1 or 0). The Boolean function can be used to represent a logical scenario. Sometimes the functions can be minimized to lowest possible number of variables. In this section we will discuss boolean function with an example. We will also derive a truth-table and an equivalent gate level implementation.
Next, we will discuss the equivalent truth table for the boolean function F1.
Resources
Digital design resources
Clock Domain Crossing Discussion with
rtl & testbench example.
Rate change(asynchronous) FIFO design and fifo depth calculation.
Half-adder, Full-adder, 4-bit binary adder , adder-subtractor circuit, overflow with rtl & testbench. Binary Multiplier, Parity error TT
Arithmetic, logical, shift micro-operations. Stack organization, LIFO, RPN discussion.
VHDL rtl - Synchronous flip-flop, latch, shim to improve timing and counter example
RTL coding guidelines. ICG cell, Assertions, $assertkill, levels.
Digital design Interview questions.
FPGA Interview. FPGA flow.
Guide to Graduate studies in US
Pipeline vs. Parallel processing.
Next, we will discuss the equivalent gate level Implementation for Function F1. The
circuit is most optimized implementation of the boolean function. F1 = (x + y)z’