Home.Verilog.Digital Design.Digital Basics.Python.RF Basics.
Previous.
Next.
Custom Search

Legal Disclaimer

Chip Designing for ASIC/ FPGA Design engineers and Students
FULLCHIPDESIGN
Digital-logic Design...  Dream for many students… start learning front-end…

Legal Disclaimer

@TYH :- 4G LTE Long Term Evolution Tutorial, CloudComputing
PICS
Verilog Tutorial.
Get Noticed:- Submit your own content to be published on fullchipdesign.com

Send it to fullchip@gmail.com

Computer Organization.
 Memory Organization.
 Cache Organization.
 Interrupt controller.
Digital Basics Tutorial.
Ground Bounce causes and prevention
Lets discuss ground bounce with the help of circuit below.
In the the circuit above the conductor 2 is connected to ground rail and expected voltage across the conductor is 0V. But in real circuits the conductor 2 itself has inductance. This inductance results in voltage (ground bounce) when current flows across the conductor.  The unintended voltage or ground bounce can propagate to circuits and can cause issues.

Steps to reduce ground bounce in circuits.
 



1. Decrease the inductance of conductor 2.
 2. Increase isolation capacitance.   
I
V
circuit
Conductor 2
Conductor 1
Ground rail
Clock Crossing.
Async FIFO.
Half Adder.
Full Adder.
Binary Adder.
Overflow.
Overflow Det.
Adder-Subtractor.
Multiplier.
Parity check.
RTL guidelines.
NAND to INVERTER.
VHDL.
RTL.
Arith Micro-ops.
Stack Org.
Parallel proc..
Pipeline proc.
CMOS Intro.