Synchronous Memory implementation to infer FPGA sync ram blocks.

On this page we are going to discuss a typical coding style to avoid implementation of memory using logic cells and instead infer memory RAM from FPGA resources. The most common technique is to not use reset condition in synchronous memory load statements in Verilog always block.

Following is a implement of synchronous RAM (Random Access Memory) block to infer FPGA Rams. Also provide is a test-bench to validate it.

Memory Diagram implementation details

~\Documents\fullchip\python\mysite\webpages\templates\webpages\test.v.html

module mem_ram_sync(
    clk,
    rst,
    read_rq,
    write_rq,
    rw_address,
    write_data,
    read_data
);
input           clk;
input           rst;
input           read_rq;
input           write_rq;
input[5:0]      rw_address;
input[7:0]      write_data;
output[7:0]     read_data;
reg[7:0]     read_data;
integer out, i;
// Declare memory 64x8 bits = 512 bits or 64 bytes
reg [7:0] memory_ram_d [63:0];
reg [7:0] memory_ram_q [63:0];
// Use positive edge of clock to read the memory
// Implement cyclic shift right
always @(posedge clk)
begin
        for (i=0;i<64; i=i+1)
             memory_ram_q[i] <= memory_ram_d[i];
end

always @(*)
begin
    for (i=0;i<64; i=i+1)
        memory_ram_d[i] = memory_ram_q[i];
    if (write_rq && !read_rq)
        memory_ram_d[rw_address] = write_data;
    if (!write_rq && read_rq)
        read_data = memory_ram_q[rw_address];
end
endmodule

In order to validate the verilog ram memory implementation we will implement a model in verilog test-bench to generate the controls. The way we are going to model it is as follows.

First we are going to fill in the memory with write only commands. The data we are going to write will be random. After filling in the memory, we will enable reads. During reads we will request random addresses between 0 and 63. We will dump both read and write data in text files. Links to test-bench, write data/memory contents, read data and analysis.