Chip Designing for ASIC/ FPGA Design engineers and Students

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Digital-logic Design...  Dream for many students… start learning front-end…

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Computer Organization.
Memory Organization.
Cache Organization.
Interrupt controller.

Arithmetic overflow related questions:-

Q1. What is arithmetic overflow scenario? Can you explain overflow in following example? Add two signed magnitude numbers -70 and -90.

Q2. Which  of the following statements are true for overflow?
A. Adding two positive numbers.
B. Adding a positive and a negative numbers.
C. Adding two negative numbers.  

Refer overflow section for hints for  above questions.  

Complement and signed numbers questions.

Q1. Convert a binary number 111001101 into 1’s complement form.

Q2. Convert the binary number 111001101 into 2’s complement.

Q.3 How do represent a number -23 in signed arithmetic?

Q.4 What is BCD ? How is it different  than binary numbers.?

Q.5 Discuss binary addition example 599 and 984.

Hint:-
Q1 1’s complement, Q2 2’s complement, Q3 Signed Arithmetic,
Q4 & Q5 BCD addition example.

Boolean functions related questions.
Q. Draw a truth-table and circuit for following boolean function? F = (x +y) z’  Hint: To solve review digital basics section.

Q. Difference between minterms and maxterms? Hint refer sections Boolean functions and minterms/maxterm.

Resources

Clock Domain Crossing Discussion with rtl & testbench

Rate change (asynchronous) FIFO design and fifo depth calculation.

Half-adder, Full-adder, 4-bit binary adder , adder-subtractor circuit, overflow with rtl & testbench. Binary Multiplier, Parity error TT
Arithmetic, logical, shift micro-operations. Stack organization, LIFO, RPN discussion.
VHDL rtl - Synchronous flip-flop, latch, shim to improve timing and counter example

RTL coding guidelines. ICG cell, Assertions, $assertkill, levels.
Digital design Interview questions.
FPGA Interview. FPGA flow.
Guide to Graduate studies in US

Pipeline vs. Parallel processing.

Misc. Verilog RTL examples:-
Binary to Gray Code conversion
File read write operations.
Clock domain crossing.
Half-adder, Full-adder, Tri-state buffer .
Verilog testbench to validate half-adder, full-adder and tri-state buffer.

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Overflow

Binary adder-subtractor circuit

Full-adder RTL & test-bench

Interview Questions. Main, FPGA, Digital