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Q2. Which of the following statements are true to generate a result with overflow?

A. Adding two positive numbers.

B. Adding a positive and a negative numbers.

C. Adding two negative numbers.

Hint: Refer -7 to +7 signed numbers topic.

Refer overflow section for hints for above questions.

A. Adding two positive numbers.

B. Adding a positive and a negative numbers.

C. Adding two negative numbers.

Hint: Refer -

Refer overflow section for hints for above questions.

Digital logic Interview questions

Complement and signed numbers questions.

Q1. Convert a binary number 111001101 into 1’s complement form.

Q2. Convert the binary number 111001101 into 2’s complement.

Q.3 How do represent a number -23 in signed arithmetic?

Q.4 What is BCD ? How is it different than binary numbers.?

Q.5 Discuss binary addition example 599 and 984.

Hint:- Q1 1’s complement, Q2 2’s complement, Q3 Signed Arithmetic, Q4 & Q5 BCD addition example.

Q1. Convert a binary number 111001101 into 1’s complement form.

Q2. Convert the binary number 111001101 into 2’s complement.

Q.3 How do represent a number -

Q.5 Discuss binary addition example 599 and 984.

Hint:-

Boolean functions related questions.

Q. Draw a truth-table and circuit for following boolean function? F = (x +y) z’ Hint: To solve review digital basics section.

Q. Difference between minterms and maxterms? Hint refer sections Boolean functions and minterms/maxterm.

Q. Draw a truth-

Resources

Clock Domain Crossing Discussion with rtl & testbench

Rate change (asynchronous) FIFO design and fifo depth calculation.

Half-adder , Full-adder , 4-bit binary adder , adder-subtractor circuit, overflow with rtl & testbench. Binary Multiplier, Parity error TT

Arithmetic, logical, shift micro-operations . Stack organization, LIFO, RPN discussion.

VHDL rtl - Synchronous flip-flop , latch, shim to improve timing and counter example

RTL coding guidelines. ICG cell, Assertions, $assertkill, levels.

Digital design Interview questions.

FPGA Interview. FPGA flow.

Guide to Graduate studies in US

Pipeline vs. Parallel processing.

Clock Domain Crossing Discussion with rtl & testbench

Rate change (asynchronous) FIFO design and fifo depth calculation.

Half-

VHDL rtl -

Digital design Interview questions.

FPGA Interview. FPGA flow.

Guide to Graduate studies in US

Pipeline vs. Parallel processing.

More Interview Questions. Main, FPGA, Digital Fundamentals

Arithmetic overflow related questions:-

Q1. What is arithmetic overflow scenario? Can you explain overflow in following example?
Add two signed magnitude numbers -

Q2. Can you extend above circuit to include carry from previous addition.?

Q3. Is it possible to reuse the circuit to add 2 bits for binary addition of two registers?

Q4. Do you a way to implement a circuit which can be used either as a adder or a
subtractor. Hint: Q1 Half-

Questions related to binary addition, subtraction of Registers.

Q1. Can you draw a digital circuit using gates to add two bits?

LTE - Long Term Evolution topics from here

Solved Examples for 3 variable Kmaps

1. F(x,y,z) = (0,1,6,7) - Minimization, on this page.

2. F(x,y,z) = (0,1,4,5,6,7) - Minimization from here.

3. F(x,y,z) = (3,4,6,7) - Minimization from here.

4. F(x,y,z) = (0,1,2,3,4,5,6,7) - Minimization from here.

1. F(x,y,z) = (0,1,6,7) -

Q How you do gate conversions ? Using Universal NAND Gate.

Derive AND gate from NAND gate.

Derive OR gate from NAND gate

Derive XOR gate from NAND gate.

Derive AND gate from NAND gate.

Derive OR gate from NAND gate

Derive XOR gate from NAND gate.