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Universal Gates -AND from NAND

Digital Logic fundamentals @ fcd

Binary number discussion, 1 and 2 complement discussion,

Binary arithmetic, Signed Magnitude, overflow, examples

Gray coding, Binary coded digital (BCD) coding, BCD addition

Digital logic gates basic (AND, OR, XOR, NOT) and derived (NAND, NOR and XNOR). Drive XOR from NAND gates. Drive XOR from NOR gates. Discussion of Boolean Algebra with examples.

Duality Principle, Huntington Postulates, Theorems of Boolean Algebra - discussion with examples, Boolean Functions, Canonical and Standard Forms, Minterms and Maxterms Sum of Minterms, Product of Maxterms or Canonical Forms,

Karnaugh map or K-map discussion 2, 3, ,4 and 5 var’s Prime Implicant & Gate level minimization examples. Digital basics tutorial

Binary number discussion, 1 and 2 complement discussion,

Binary arithmetic, Signed Magnitude, overflow, examples

Gray coding, Binary coded digital (BCD) coding, BCD addition

Digital logic gates basic (AND, OR, XOR, NOT) and derived (NAND, NOR and XNOR). Drive XOR from NAND gates. Drive XOR from NOR gates. Discussion of Boolean Algebra with examples.

Duality Principle, Huntington Postulates, Theorems of Boolean Algebra -

Introduction to Verilog RTL

Verilog Operators.

Initial Statements in verilog.

Clock and Reset generation.

Blocking vs. Non-blocking Statements.

Conditional Statements & ‘always’ block.

Counter Implementation.

File Operations - $fopen, $fclose, $fdisplay, $fscanf

Read binary or hex format files - $readmemh, $readmemb. FOR Loop use in verilog code example

Verilog Operators.

Initial Statements in verilog.

Clock and Reset generation.

Blocking vs. Non-

Conditional Statements & ‘always’ block.

Counter Implementation.

File Operations -

Read binary or hex format files -

X (Input 1)

Y (Input 2)

Z (Output)

Z2 (identical to Z

Final Output

0

0

1

1

0

0

1

1

1

0

1

0

1

1

0

1

1

0

0

1

AND Gate

A (Input 1)

B (Input 2)

Z (Output)

0

0

0

0

1

0

1

0

0

1

1

1

NAND Gate

X (Input 1)

Y (Input 2)

Z (Output)

0

0

1

0

1

1

1

0

1

1

1

0

Steps to generate equivalent AND gate from NAND gate. From the truth-tables of NAND and AND gate the above circuit is derived. It represents the desired connectivity. The details are further discussed in truth table below.

Interview Questions. Main, FPGA, Digital Fundamentals

Misc. Verilog RTL examples:-

Binary to Gray Code conversion

File read write operations. Clock domain crossing. Half-adder , Full-adder , Tri-state buffer . Verilog testbench to validate half-adder, full-adder and tri-state buffer.

VERILOG HOME

File read write operations. Clock domain crossing. Half-

VERILOG HOME

Interview Questions. Main, FPGA, Digital Fundamentals

LTE - Long Term Evolution topics from here

NAND

NAND

X

Y

Equivalent AND GATE