Blocking statements are declared using ‘=’ operator. For these statements the registers are updated only when the previous assignment is updated. All the events in this case statements happens only in one sequence.
Verilog Blocking & Non-blocking statements
So At negative edge of reset. The events will update concurrently R1,R2,R3,R4,R5 Otherwise, At positive edge of clock. The events will update concurrently C1,C2,C3,C4,C5
Non-Blocking statements are declared using ‘<=’ operator. For these statements the registers are updated concurrently at the rising edge of the clock or at reset.
Example - Case statements are used in RTL design to model states in Finite State
Machine and for generating conditional statements based on value of a particular
register. Case statement implementation is shown on left.
Example - Counters are extensively used in synchronous RTL. In current implementation, its used for keeping track of packets.