SystemVerilog constructs always_comb and always_ff.
always_comb : This construct uniquely differentiates Verilog always block for just
combinational logic. So use only blocking assignments within this blocks. All statements
are executed one after another. Example next
module casetest ( …. );
3'b00?: w_ena_memory_block1: = 1’b1;
3'b01?: w_ena_memory_block2 = 1'b1;
3'b1??: w_ena_memory_block3 = 1'b1;
default: w_ena_memory_block3 = 1'b1;
always_ff: This construct uniquely differentiates Verilog always block for just synchronous
logic. So use only non-blocking assignments within this blocks. All statements are
executed in parallel in presence of clock. So when these constructs are used, flip-flops
are inferred for all preset_state to next_state assignments. Example Next.
In system verilog two different syntax for always blocks can be used to limit the
logical usage within code structure. The two new syntax’s are always_ff and always_comb.
These constructs allow in simple differentiation of combinational logic from sequential