Chip Designing for ASIC/ FPGA Design engineers and Students
Digital-logic Design... Dream for many students… start learning front-end…
The K-map for 3 variables is plotted above. You will notice the column for 11 and 10 is inter-changed. This is done to allow only one variable to change across adjacent cells. This adjustment in columns allows in minimization of logic mapped into tables.
Any adjacent 1, 2, 4 or 8 cells can be grouped to find a minimized logic value.
Following plot will show grouping of adjacent cells.
The two step minimization equation is shown below.
With reference to the table above the cells under the dotted box’s can be combined to come up with following reduced equation.
F = (x’yz+ xyz) + (xyz’ + xy’z’)
F = (yz + xz’) ... Final Answer.
1. F(x,y,z) = (0,1,6,7) - Minimization, on this page.
2. F(x,y,z) = (0,1,4,5,6,7) - Minimization from here.
3. F(x,y,z) = (3,4,6,7) - Minimization from here.
4. F(x,y,z) = (0,1,2,3,4,5,6,7) - Minimization from here.
MINIMIZATION USING THREE VARIABLE KARNAUGH MAP