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Chip Designing for ASIC/ FPGA Design engineers and Students

FULLCHIPDESIGN

Digital-logic Design... Dream for many students… start learning front-end…

3 variable K-

Minimize following

F(x,y,z) = (3,4,6,7)

Above is a common format of representing the K-

00

01

4

5

11

10

7

6

x’y’z’ = 0

x’y’z = 0

x’yz = 1

x’yz’ = 0

xy’z’ = 1

xy’z = 0

xyz = 1

xyz’ = 1

0

1

x

yz

Interview Questions. Main, FPGA, Digital Fundamentals

The K-map for 3 variables is plotted above. You will notice the column for 11 and 10 is inter-changed. This is done to allow only one variable to change across adjacent cells. This adjustment in columns allows in minimization of logic mapped into tables.

Any adjacent 1, 2, 4 or 8 cells can be grouped to find a minimized logic value.

Following plot will show grouping of adjacent cells.

Any adjacent 1, 2, 4 or 8 cells can be grouped to find a minimized logic value.

Following plot will show grouping of adjacent cells.

00

01

4

5

11

10

7

6

x’y’z’ = 0

x’y’z = 0

x’yz = 1

x’yz’ = 0

xy’z’ = 1

xy’z = 0

xyz = 1

xyz’ = 1

0

1

x

yz

The two step minimization equation is shown below.

With reference to the table above the cells under the dotted box’s can be combined to come up with following reduced equation.

F = (x’yz+ xyz) + (xyz’ + xy’z’)

F = (yz + xz’) ... Final Answer.

With reference to the table above the cells under the dotted box’s can be combined to come up with following reduced equation.

F = (x’yz+ xyz) + (xyz’ + xy’z’)

F = (yz + xz’) ... Final Answer.

x’y’z’

x’y’z

x’yz

x’yz’

xy’z’

xy’z

xyz

xyz’

x’y’z

x’yz

x’yz’

xy’z’

xy’z

xyz

xyz’

Solved Examples

1. F(x,y,z) = (0,1,6,7) - Minimization, on this page.

2. F(x,y,z) = (0,1,4,5,6,7) - Minimization from here.

3. F(x,y,z) = (3,4,6,7) - Minimization from here.

4. F(x,y,z) = (0,1,2,3,4,5,6,7) - Minimization from here.

1. F(x,y,z) = (0,1,6,7) -

MINIMIZATION USING THREE VARIABLE KARNAUGH MAP